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| ltc1403/ltc1403a 1 1403fb block diagram features applications description serial 12-bit/14-bit, 2.8msps sampling adcs with shutdown the ltc ? 1403/ltc1403a are 12-bit/14-bit, 2.8msps se- rial adcs with differential inputs. the devices draw only 4.7ma from a single 3v supply and come in a tiny 10-lead ms package. a sleep shutdown feature lowers power consumption to 10w. the combination of speed, low power and tiny package makes the ltc1403/ltc1403a suitable for high speed, portable applications. the 80db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the devices convert 0v to 2.5v unipolar inputs differentially. the absolute voltage swing for +a in and Ca in extends from ground to the supply voltage. the serial interface sends out the conversion results during the 16 clock cycles following conv for compatibility with standard serial interfaces. if two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8msps can be achieved with a 50.4mhz clock. 2.8msps conversion rate low power dissipation: 14mw 3v single supply operation C40c to 125c guaranteed operation 2.5v internal bandgap reference can be overdriven 3-wire serial interface sleep (10w) shutdown mode nap (3mw) shutdown mode 80db common mode rejection 0v to 2.5v unipolar input range tiny 10-lead ms package automotive communications data acquisition systems uninterrupted power supplies multiphase motor control multiplexed data acquisition , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. + 1 2 7 3 4 s & h gnd exposed pad ltc1403a v ref 10 f a in a in + 14-bit adc 3v 10 f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdoconv sck 1403a ta01 5 6 11 frequency (mhz) 0.1 ?0 thd, 2nd, sfdr, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 1403a ta02 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd, sfdr 2nd, 3rd and sfdr vs input frequency downloaded from: http:///
ltc1403/ltc1403a 2 1403fb package/order information absolute maximum ratings supply voltage (v dd ) ..................................................4v analog input voltage (note 3) ....................................C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ...................C0.3v to (v dd + 0.3v) power dissipation .............................................. 100mw operation temperature range ltc1403c/ltc1403ac ............................. 0c to 70c ltc1403i/ltc1403ai ........................... C40c to 85c ltc1403h/ltc1403ah ...................... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1, 2,) 12 3 4 5 a in + a in v ref gndgnd 109 8 7 6 convsck sdo v dd gnd top view 11 mse package 10-lead plastic msop t jmax = 150c, ja = 40c/w exposed pad is gnd (pin 11) must be soldered to pcb order part number mse part marking ltc1403cmse ltc1403imse ltc1403hmse ltc1403acmse ltc1403aimse ltc1403ahmse ltbdn ltbdp ltbdp ltadf ltafd ltafd order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. converter characteristics parameter conditions ltc1403 ltc1403h ltc1403a ltc1403ah units min typ max min typ max min typ max min typ max resolution (no missing codes) 12 12 14 14 bits integral linearity error (notes 4, 5, 18) C2 0.25 2 C2 0.25 2 C4 0.5 4 C4 0.5 4 lsb offset error (notes 4, 18) C10 1 10 C20 2 20 C20 2 20 C30 2 30 lsb gain error (note 4, 18) C30 5 30 C40 5 40 C60 10 60 C80 10 80 lsb gain tempco internal reference (note 4) external reference 15 1 15 1 15 1 15 1 ppm/cppm/c the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. with internal reference. v dd = 3v symbol parameter conditions min typ max units v in analog differential input range (notes 3, 9) 2.7v v dd 3.3v 0 to 2.5 v v cm analog common mode + differential input range (note 10) 0 to v dd v i in analog input leakage current 1 a c in analog input capacitance 13 pf t acq sample-and-hold acquisition time (note 6) 39 ns t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ps cmrr analog input common mode rejection ratio f in = 1mhz, v in = 0v to 3v f in = 100mhz, v in = 0v to 3v C60C15 dbdb analog input the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v downloaded from: http:/// ltc1403/ltc1403a 3 1403fb the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v dynamic accuracy symbol parameter conditions ltc1403/ltc1403h ltc1403a/ltc1403ah units min typ max min typ max sinad signal-to-noise plus distortion ratio 100khz input signal1.4mhz input signal 1.4mhz input signal (h grade) 100khz input signal, external v ref = 3.3v, v dd 3.3v 750khz input signal, external v ref = 3.3v, v dd 3.3v 6867 70.570.5 70.5 7272 7069 73.573.5 73.0 76.3 76.3 dbdb db db db thd total harmonic distortion 100khz first 5 harmonics1.4mhz first 5 harmonics C87 C83 C76 C90 C86 C78 dbdb sfdr spurious free dynamic range 100khz input signal1.4mhz input signal C87C83 C90C86 dbdb imd intermodulation distortion 1.25v to 2.5v 1.25mhz into a in + , 0v to 1.25v, 1.2mhz into a in C C82 C82 db code-to-code transition noise v ref = 2.5v (note 18) 0.25 1 lsb rms full power bandwidth v in = 2.5v p-p , sdo = 11585lsb p-p (note 15) 50 50 mhz full linear bandwidth s/(n + d) 68db 5 5 mhz symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.3v 2.4 v v il low level input voltage v dd = 2.7v 0.6 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance 5p f v oh high level output voltage v dd = 3v, i out = C200a 2.5 2.9 v v ol low level output voltage v dd = 2.7v, i out = 160a v dd = 2.7v, i out = 1.6ma 0.05 0.10 0.4 vv i oz hi-z output leakage d out v out = 0v to v dd 10 a c oz hi-z output capacitance d out 1p f i source output short-circuit source current v out = 0v, v dd = 3v 20 ma i sink output short-circuit sink current v out = v dd = 3v 15 ma the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v digital inputs and digital outputs parameter conditions min typ max units v ref output voltage i out = 0 2.5 v v ref output tempco 15 ppm//c v ref line regulation v dd = 2.7v to 3.6v, v ref = 2.5v 600 v/v v ref output resistance load current = 0.5ma 0.2 v ref settling time 2m s the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v internal reference chharacteristics downloaded from: http:/// ltc1403/ltc1403a 4 1403fb symbol parameter conditions min typ max units v dd supply voltage 2.7 3.6 v i dd positive supply voltage active mode active mode (ltc1403h, ltc1403ah) nap mode nap mode (ltc1403h, ltc1403ah) sleep mode (ltc1403, ltc1403h) sleep mode (ltc1403a, ltc1403ah) 4.75.2 1.1 1.2 22 78 1.51.8 1510 mama ma ma aa p d power dissipation active mode with sck in fixed state (hi or lo) 12 mw the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 17) power requirements symbol parameter conditions min typ max units f sample(max) maximum sampling frequency per channel (conversion rate) 2.8 mhz t throughput minimum sampling period (conversion + acquisiton period) 357 ns t sck clock period (notes 16) 19.8 10000 ns t conv conversion time (note 6) 16 18 sclk cycles t 1 minimum positive or negative sclk pulse width (note 6) 2 ns t 1 conv to sck setup time (notes 6, 10) 3 ns t 3 nearest sck edge before conv (note 6) 0 ns t 4 minimum positive or negative conv pulse width (note 6) 4 ns t 5 sck to sample mode (note 6) 4 ns t 6 conv to hold mode (notes 6, 11) 1.2 ns t 7 16th sck to conv interval (affects acquisition period) (notes 6, 7, 13) 45 ns t 8 minimum delay from sck to valid bits 0 through 13 (notes 6, 12) 8 ns t 9 sck to hi-z at sdo (notes 6, 12) 6 ns t 10 previous sdo bit remains valid after sck (notes 6, 12) 2 ns t 12 v ref settling time after sleep-to-wake transition (notes 6, 14) 2 ms the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 3v timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: when these pins are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or greater than v dd without latchup. note 4: offset and full-scale speci? cations are measured for a single-ended a in + input with a in C grounded and using the internal 2.5v reference. note 5: integral linearity is tested with an external 2.55v reference and is de? ned as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. the deviation is measured from the center of quantization band. note 6: guaranteed by design, not subject to test. note 7: recommended operating conditions. note 8: the analog input range is de? ned for the voltage difference between a in + and a in C . note 9: the absolute voltage at a in + and a in C must be within this range. note 10: if less than 3ns is allowed, the output data will appear one clock cycle later. it is best for conv to rise half a clock before sck, when running the clock at rated speed. note 11: not the same as aperture delay. aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the conv to hold mode delay. note 12: the rising edge of sck is guaranteed to catch the data coming out into a storage latch.note 13: the time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. note 14: the internal reference settles in 2ms after it wakes up from sleep mode with one or more cycles at sck and a 10f capacitive load. note 15: the full power bandwidth is the frequency where the output code swing drops to 3db with a 2.5v p-p input sine wave. note 16: maximum clock period guarantees analog performance during conversion. output data can be read without an arbitrarily long clock.note 17: v dd = 3v, f sample = 2.8msps. note 18: the ltc1403a is measured and speci? ed with 14-bit resolution (1lsb = 152v) and the ltc1403 is measured and speci? ed with 12-bit resolution (1lsb = 610v). downloaded from: http:/// ltc1403/ltc1403a 5 1403fb typical performance characteristics enobs and sinad vs input frequency thd, 2nd and 3rd vs input frequency sfdr vs input frequency snr vs input frequency 98khz sine wave 4096 point fft plot 1.3mhz sine wave 4096 point fft plot 1.4mhz input summed with 1.56mhz input imd 4096 point fft plot differential linearityvs output code integral linearity vs output code t a = 25c, v dd = 3v (ltc1403a) frequency (mhz) 0.1 10.0 enobs (bits) sinad (db) 11.0 12.0 1 10 100 1403a g01 9.0 9.5 10.5 11.5 8.58.0 62 68 74 56 59 65 71 5350 frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 1403a g02 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd frequency (mhz) 0.1 68 sfdr (db) 56 44 1 10 100 1403a g17 80 7462 50 86 92 98 104 frequency (mhz) 0.1 62 snr (db) 56 50 1 10 100 1403a g03 68 6559 53 71 74 frequency (hz) 0 350k 700k 1.05m 1.4m magnitude (db) 1403a g04 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 2.8msps frequency (hz) magnitude (db) 1403a g05 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 350k 700k 1.05m 1.4m 2.8msps frequency (hz) magnitude (db) 1403a g06 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 0 350k 700k 1.05m 1.4m 2.8msps output code 0 8192 4096 12288 16383 differential linearity (lsb) 1403a g13 1.00.8 0.6 0.4 0.2 0 ?.2?.4 ?.6 ?.8 ?.0 output code 0 8192 4096 12288 16383 integral linearity (lsb) 1403a g14 43 2 1 0 ?? ? ? downloaded from: http:/// ltc1403/ltc1403a 6 1403fb typical performance characteristics t a = 25c, v dd = 3v (ltc1403a) differential and integral linearity vs conversion rate sinad vs conversion rate 2.5v p-p power bandwidth cmrr vs frequency psrr vs frequency reference voltage vs load current reference voltage vs v dd v dd supply current vs conversion rate conversion rate (msps) 2.0 2.2 3.0 2.6 3.8 4.0 2.8 2.4 3.4 3.2 linearity (lsb) 1403a g15 54 3 2 1 0 ?? ? ? ? max inl 18 clocks per conversion max dnl min dnl min inl 3.6 conversion rate (msps) 2.0 2.2 3.0 2.6 3.8 4.0 2.8 2.4 3.4 3.6 3.2 s/(n+d) 1403a g16 8079 78 77 76 75 74 73 72 71 70 external v ref = 3.3v f in ~f s /40 internal v ref = 2.5v f in ~f s /40 internal v ref = 2.5v f in ~f s /3 external v ref = 3.3v f in ~f s /3 frequency (hz) 1m 10m 100m 1g ?8 amplitude (db) ?2 ? 0 1403a g07 ?4?0 ?6 6 12 frequency (hz) 100 cmrr (db) 0 ?0?0 ?0 ?0 ?00?20 1k 10k 100k 1m 1403a g08 10m 100m frequency (hz) 11 0 ?0 psrr (db) ?5 ?0 ?5 ?0 100 1k 10k 100k 1m 1403a g09 ?5 ?0 ?5 ?0 ?5 load current (ma) 0.4 0.8 1.2 1.6 1403a g10 2.0 0.2 0 0.6 1.0 1.4 1.8 2.4890 v ref (v) 2.4894 2.4898 2.49022.4892 2.4896 2.4900 v dd (v) 2.4890 v ref (v) 2.4894 2.4898 2.49022.4892 2.4896 2.4900 2.8 3.0 3.2 3.4 1403a g11 2.6 3.6 conversion rate (msps) 0 2.0 1.6 1.2 0.8 0.4 2.8 3.2 2.4 3.6 4.0 v dd supply current (ma) 1403a g12 6.05.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25c, v dd = 3v (ltc1403 and ltc1403a) downloaded from: http:/// ltc1403/ltc1403a 7 1403fb block diagram pin functions a in + (pin 1): noninverting analog input. a in + operates fully differentially with respect to a in C with a 0v to 2.5v differential swing and a 0v to v dd common mode swing. a in C (pin 2): inverting analog input. a in C operates fully differentially with respect to a in + with a C2.5v to 0v differential swing and a 0v to v dd common mode swing. v ref (pin 3): 2.5v internal reference. bypass to gnd and to a solid analog ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). can be overdriven by an external reference between 2.55v and v dd . gnd (pins 5, 6, 11): ground and exposed pad. these ground pins and the exposed pad must be tied directly to the solid ground plane under the part. keep in mind that analog signal currents and digital output signal currents ? ow through these pins. v dd (pin 7): 3v positive supply. this single power pin supplies 3v to the entire chip. bypass to gnd and to a solid analog ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). keep in mind that internal analog currents and digital output signal currents ? ow through this pin. care should be taken to place the 0.1f bypass capacitor as close to pins 6 and 7 as possible. sdo (pin 8): three-state serial data output. each of output data words represents the difference between a in + and a in C analog inputs at the start of the previous conversion.sck (pin 9): external clock input. advances the conver- sion process and sequences the output data on the rising edge. responds to ttl (3v) and 3v cmos levels. one or more pulses wake from sleep. conv (pin 10): convert start. holds the analog input signal and starts the conversion on the rising edge. responds to ttl (3v) and 3v cmos levels. two pulses with sck in ? xed high or ? xed low state start nap mode. four or more pulses with sck in ? xed high or ? xed low state start sleep mode. 1403a bd + 1 2 7 3 4 s & h gnd exposed pad ltc1403a v ref 10 f a in a in + 14-bit adc 3v 10 f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdoconv sck 5 6 11 downloaded from: http:/// ltc1403/ltc1403a 8 1403fb timing diagram ltc1403 timing diagram sck conv internal s/h status sdo t 7 t 3 t 1 1 17 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 10 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion *bits marked "x" after d0 should be ignored. t throughput 1403a td01 d11 d10 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x d9 sample 1 ltc1403a timing diagram sck conv internal s/h status sdo t 7 t 3 t 1 1 17 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 10 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion t throughput 1403a td01b d13 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 sample 1 nap mode and sleep mode waveforms slk conv nap sleep v ref t 1 t 12 t 1 note: nap and sleep are internal signals 1403a td02 sck to sdo delay t 8 t 10 sck sdo 1403a td03 v ih v oh v ol t 9 sck sdo v ih 90%10% downloaded from: http:/// ltc1403/ltc1403a 9 1403fb applications information driving the analog input the differential analog inputs of the ltc1403/ltc1403a are easy to drive. the inputs may be driven differentially or as a single-ended input (i.e., the a in C input is grounded). both differential analog inputs, a in + with a in C , are sampled at the same instant. any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1403/ltc1403a inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer ampli? er must be used. the main requirement is that the ampli? er driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). also keep in mind while choosing an input ampli? er, the amount of noise and harmonic distor- tion added by the ampli? er. choosing an input amplifier choosing an input ampli? er is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the ampli? er from charging the sampling capacitor, choose an ampli? er that has a low output impedance (<100 ) at the closed-loop bandwidth frequency. for example, if an ampli? er is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1403/ltc1403a will depend on the application. generally, applications fall into two categories: ac applications where dynamic speci? cations are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1403/ltc1403a. (more detailed information is available in the linear technology databooks and on the linearview tm cd-rom.) ltc ? 1566-1: low noise 2.3mhz continuous time low- pass filter. lt1630: dual 30mhz rail-to-rail voltage fb ampli? er. 2.7v to 15v supplies. very high a vol , 500v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k , v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail performance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage fb ampli? er. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applications with a single 5v supply. thd and noise are C93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k , v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1813: dual 100mhz 750v/s 3ma voltage feedback ampli? er. 5v to 5v supplies. distortion is C86db to 100khz and C77db to 1mhz with 5v supplies (2v p-p into 500 ). excellent part for fast ac applications with 5v supplies. lt1801: 80mhz gbwp, C75dbc at 500khz, 2ma/ampli? er, 8.5nv/ ? h ? z. lt1806/lt1807: 325mhz gbwp, C80dbc distortion at 5mhz, unity-gain stable, r-r in and out, 10ma/ampli- ? er, 3.5nv/ ? h ? z. lt1810: 180mhz gbwp, C90dbc distortion at 5mhz, unity- gain stable, r-r in and out, 15ma/ampli? er, 16nv/ ? h ? z. lt1818/lt1819: 400mhz, 2500v/s,9ma, single/dual voltage mode operational ampli? er. lt6200: 165mhz gbwp, C85dbc distortion at 1mhz, unity-gain stable, r-r in and out, 15ma/ampli? er, 0.95nv/ ? h ? z. lt6203: 100mhz gbwp, C80dbc distortion at 1mhz, unity- gain stable, r-r in and out, 3ma/ampli? er, 1.9nv/ ? h ? z. lt6600-10: ampli? er/filter differential in/out with 10mhz cutoff. linearview is a trademark of linear technology corporation. downloaded from: http:/// ltc1403/ltc1403a 10 1403fb applications information 10 f 11 3 a in ltc1403/ ltc1403a a in + 47pf 2 1 51 gnd v ref 1403a f01 figure 1. rc input filter input filtering and source impedance the noise and the distortion of the input ampli? er and other circuitry must be considered since they will add to the ltc1403/ltc1403a noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 50mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. for example, figure 1 shows a 47pf capacitor from a in + to ground and a 51 source resistor to limit the input bandwidth to 47mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole ? lter is required. high external source resistance, combined with the 13pf of input capacitance, will reduce the rated 50mhz bandwidth and increase acquisition time beyond 39ns. input range the analog inputs of the ltc1403/ltc1403a may be driven fully differentially with a single supply. each input may swing up to 3v p-p individually. in the conversion range, the noninverting input of each channel is always up to 2.5v more positive than the inverting input of each channel. the 0v to 2.5v range is also ideally suited for single-ended input use with single supply applications. the common mode range of the inputs extend from ground to the supply voltage v dd . if the difference between the a in + and a in C inputs exceeds 2.5v, the output code will stay ? xed at all ones and if this difference goes below 0v, the ouput code will stay ? xed at all zeros. internal reference the ltc1403/ltc1403a has an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5v to obtain 2.5v input span. the reference ampli? er output v ref , (pin 3) must be bypassed with a capacitor to ground. the reference ampli? er is stable with capacitors of 1f or greater. for the best noise performance, a 10f ceramic or a 10f tantalum in parallel with a 0.1f ceramic is recommended. the v ref pin can be overdriven with an external reference as shown in figure 2. the voltage of the external reference must be higher than the 2.5v of the class a pull-up output of the internal reference. the recom- mended range for an external reference is 2.55v to v dd . an external reference at 2.55v will see a dc quiescent load of 0.75ma and as much as 3ma during conversion. gnd ltc1403/ ltc1403a v ref 10 f 11 3 3v ref 1403a f02 figure 2 downloaded from: http:/// ltc1403/ltc1403a 11 1403fb applications information input span versus reference voltage the differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output v ref at pin 3, and the voltage at the ground (exposed pad ground). the differential input range of the adc is 0v to 2.5v when using the internal reference. the internal adc is referenced to these two nodes. this relationship also holds true with an external reference. differential inputs the ltc1403/ltc1403a has a unique differential sample- and-hold circuit that allows inputs from ground to v dd . the adc will always convert the unipolar difference ofa in + C a in C , independent of the common mode voltage at the inputs. the common mode rejection holds up at extremely high frequencies, see figure 3. the only require- ment is that both inputs not go below ground or exceed v dd . integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are largely independent of the common mode voltage. however, the offset error will vary. the change in offset error is typically less than 0.1% of the common mode voltage. figure 4 shows the ideal input/output characteristics for the ltc1403/ltc1403a. the code transitions occur mid- way between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is natural binary with 1lsb = 2.5v/16384 = 153v for the ltc1403a, and 1lsb = 2.5v/4096 = 610v for the ltc1403. the ltc1403a has 1lsb rms of random white noise. figure 3 figure 4 frequency (hz) 100 cmrr (db) 0 ?0?0 ?0 ?0 ?00?20 1k 10k 100k 1m 1403a f03 10m 100m cmrr vs frequency input voltage (v) unipolar output code 1403a f05 111...111111...110 111...101 000...000 000...001 000...010 fs ?1lsb 0 ltc1403/ltc1403a transfer characteristic downloaded from: http:/// ltc1403/ltc1403a 12 1403fb applications information board layout and bypassingwire wrap boards are not recommended for high resolu- tion and/or high speed a/d converters. to obtain the best performance from the ltc1403/ltc1403a, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. if optimum phase match between the inputs is desired, the length of the two input wires should be kept matched. high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in the block diagram on the ? rst page of this data sheet. for optimum performance, a 10f surface mount avx capacitor with a 0.1f ceramic is recommended for the v dd and v ref pins. alternatively, 10f ceramic chip capacitors such as murata grm235y5v106z016 may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. figure 5 shows the recommended system ground connec- tions. all analog circuitry grounds should be terminated at the ltc1403/ltc1403a gnd (pins 4, 5, 6 and exposed pad). the ground return from the ltc1403/ltc1403a (pins 4, 5, 6 and exposed pad) to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply com- mon. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. power-down modes upon power-up, the ltc1403/ltc1403a is initialized to the active state and is ready for conversion. the nap and sleep mode waveforms show the power-down modes for the ltc1403/ltc1403a. the sck and conv inputs control the power-down modes (see timing diagrams). two rising edges at conv, without any intervening rising edges at sck, put the ltc1403/ltc1403a in nap mode and the power drain drops from 14mw to 6mw. the internal reference remains powered in nap mode. one or more rising edges at sck wake up the ltc1403/ltc1403a for service very quickly, and conv can start an accurate conversion within a clock cycle. four rising edges at conv, without any figure 5. recommended layout downloaded from: http:/// ltc1403/ltc1403a 13 1403fb applications information intervening rising edges at sck, put the ltc1403/ltc1403a in sleep mode and the power drain drops from 16mw to 10w. one or more rising edges at sck wake up the ltc1403/ltc1403a for operation. the internal reference (v ref ) takes 2ms to slew and settle with a 10f load. note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. note that, for slower conversion rates, the nap and sleep modes can be used for substantial reductions in power consumption. digital interface the ltc1403/ltc1403a has a 3-wire spi (serial protocol interface) interface. the sck and conv inputs and sdo output implement this interface. the sck and conv inputs accept swings from 3v logic and are ttl compatible, if the logic swing does not exceed v dd . a detailed description of the three serial port signals follows:conversion start input (conv) the rising edge of conv starts a conversion, but subse- quent rising edges at conv are ignored by the ltc1403/ ltc1403a until the following 16 sck rising edges have occurred. it is necessary to have a minimum of 16 rising edges of the clock input sck between rising edges of conv. but to obtain maximum conversion speed, it is necessary to allow two more clock periods between conversions to allow 39ns of acquisition time for the internal adc sample- and-hold circuit. with 16 clock periods per conversion, the maximum conversion rate is limited to 2.8msps to allow 39ns for acquisition time. in either case, the output data stream comes out within the ? rst 16 clock periods to ensure compatibility with processor serial ports. the duty cycle of conv can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. a simple approach to generate conv is to create a pulse that is one sck wide to drive the ltc1403/ltc1403a and then buffer this signal with the appropriate number of inverters to ensure the correct delay driving the frame sync input of the processor serial port. it is good practice to drive the ltc1403/ltc1403a conv input ? rst to avoid digital noise interference during the sample-to-hold transition triggered by conv at the start of conversion. it is also good practice to keep the width of the low portion of the conv signal greater than 15ns to avoid introducing glitches in the front end of the adc just before the sample-and-hold goes into hold mode at the rising edge of conv. minimizing jitter on the conv input in high speed applications where high amplitude sinewaves above 100khz are sampled, the conv signal must have as little jitter as possible (10ps or less). the square wave output of a common crystal clock module usually meets this requirement easily. the challenge is to generate a conv signal from this crystal clock without jitter corruption from other digital circuits in the system. a clock divider and any gates in the signal path from the crystal clock to the conv input should not share the same integrated circuit with other parts of the system. as shown in the interface circuit examples, the sck and conv inputs should be driven ? rst, with digital buffers used to drive the serial port interface. also note that the master clock in the dsp may already be corrupted with jitter, even if it comes directly from the dsp crystal. another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10mhz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40mhz). the jitter in these pll-generated high speed clocks can be several nanoseconds. note that if you choose to use the frame sync signal generated by the dsp port, this signal will have the same jitter of the dsps master clock. serial clock input (sck) the rising edge of sck advances the conversion process and also udpates each bit in the sdo data stream. after conv rises, the third rising edge of sck starts clocking out the 12/14 data bits with the msb sent ? rst. a simple ap- proach is to generate sck to drive the ltc1403/ltc1403a downloaded from: http:/// ltc1403/ltc1403a 14 1403fb applications information figure 6. dsp serial interface to tms320c54x ? rst and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. use the falling edge of the clock to latch data from the serial data output (sdo) into your processor serial port. the 14-bit serial data will be received right justi? ed, in a 16-bit word with 16 or more clocks per frame sync. it is good practice to drive the ltc1403/ltc1403a sck input ? rst to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. unlike the conv input, the sck input is not sensitive to jitter because the input signal is already sampled and held constant. serial data output (sdo) upon power-up, the sdo output is automatically reset to the high impedance state. the sdo output remains in high impedance until a new conversion is started. sdo sends out 12/14 bits in the output data stream beginning at the third rising edge of sck after the rising edge of conv. sdo is always in high impedance mode when it is not sending out data bits. please note the delay speci? cation from sck to a valid sdo. sdo is always guaranteed to be valid by the next rising edge of sck. the 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. hardware interface to tms320c54x the ltc1403/ltc1403a is a serial output adc whose interface has been designed for high speed buffered serial ports in fast digital signal processors (dsps). figure 6 shows an example of this interface using a tms320c54x. the buffered serial port in the tms320c54x has direct access to a 2kb segment of memory. the adcs serial data can be collected in two alternating 1kb segments, in real time, at the full 2.8msps conversion rate of the ltc1403/ltc1403a. the dsp assembly code sets frame sync mode at the bfsr pin to accept an external posi- tive going pulse and the serial clock at the bclkr pin to accept an external positive edge clock. buffers near the ltc1403/ltc1403a may be added to drive long tracks to the dsp to prevent corruption of the signal to ltc1403/ ltc1403a. this con? guration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the dsp, may be needed to match the characteristic impedance of very long transmission lines. if you need to terminate the sdo transmission line, buffer it ? rst with one or two 74actxx gates. the ttl threshold inputs of the dsp port respond properly to the 3v swing from the sdo pin. 1403a f09 710 9 8 6 3-wire serial interfacelink v dd conv sck ltc1403/ltc1403a sdo v cc bfsrbclkr tms320c54x bdr gnd conv 0v to 3v logic swing clk 3v 5v b13 b12 downloaded from: http:/// ltc1403/ltc1403a 15 1403fb applications information ; 01-08-01 ******************************************************************; files: 014si.asm -> 1403a sine wave collection with serial port interface ; bvectors.asm buffered mode to avoid standard mode bug. ; s2k14ini.asm 2k buffer size. ; ? rst element at 1024, last element at 1023, two middles at 2047 and 0000 ; unipolar mode; works 16 or 64 clock frames. ; negative edge bclkr ; negative bfsr pulse ; -0 data shifted ; 1 cable from counter to conv at dut ; 2 cable from counter to clk at dut ; *************************************************************************** .width 160 .length 110 .title sineb0 bsp in auto buffer mode .mmregs .setsect .text, 0x500,0 ;set address of executable .setsect vectors, 0x180,0 ;set address of incoming 1403 data .setsect buffer, 0x800,0 ;set address of bsp buffer for clearing .setsect result, 0x1800,0 ;set address of result for clearing .text ;.text marks start of code start: ;this label seems necessary ;make sure /pwrdwn is low at j1-9 ;to turn off ac01 adc tim=#0fh prd=#0fh tcr = #10h ; stop timer tspc = #0h ; stop tdm serial port to ac01 pmst = #01a0h ; set up iptr. processor mode status register sp = #0700h ; init stack pointer. dp = #0 ; data page ar2 = #1800h ; pointer to computed receive buffer. ar3 = #0800h ; pointer to buffered serial port receive buffer ar4 = #0h ; reset record counter call sineinit ; double clutch the initialization to insure a proper sinepeek: call sineinit ; reset. the external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. wait goto wait ; ----------------buffered receive interrupt routine ------------------ breceive: ifr = #10h ; clear interrupt ? ags tc = bitf(@bspce,#4000h) ; check which half (bspce(bit14)) of buffer if (ntc) goto bufull ; if this still the ? rst half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable ; --------------mask and shift input data ---------------------------- bufull: b = *ar3+ << -0 ; load acc b with bsp buffer and shift right -0 b = #03fffh & b ; mask out the tristate bits with #03fffh ; *ar2+ = data(#0bh) ; store b to out buffer and advance ar2 pointer tc = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h if (tc) goto start ; restart if out buffer is at 1fffh goto bufull downloaded from: http:/// ltc1403/ltc1403a 16 1403fb ; -------------------dummy bsend return------------------------ bsend return_enable ;this is also a dummy return to de? ne bsend ;in vector table ? le bvectors.asm ; ----------------------- end isr ---------------------------- .copy c:\dskplus\1403\s2k14ini.asm ;initialize buffered serial port .space 16*32 ;clear a chunk at the end to mark the end ;====================================================================== ; ; vectors ; ;====================================================================== .sect vectors ;the vectors start here .copy c:\dskplus\1403\bvectors.asm ;get bsp vectors .sect buffer ;set address of bsp buffer for clearing .space 16*0x800 .sect result ;set address of result for clearing .space 16*0x800 .end ********************************************************************** * (c) copyright texas instruments, inc. 1996 * ********************************************************************** * * * file: s2k14ini.asm bsp initialization code for the c54x dskplus * * for use with 1403a in standard mode * * bspc and spc are the same in the c542 * * bspce and spce seem the same in the c542 * ********************************************************************** .title buffered serial port initialization routine on .set 1 off .set !on yes .set 1 no .set !yes bit_8 .set 2 bit_10 .set 1 bit_12 .set 3 bit_16 .set 0 go .set 0x80 ********************************************************************** * this is an example of how to initialize the buffered serial port (bsp). * the bsp is initialized to require an external clk and fsx for * operation. the data format is 16-bits, burst mode, with autobuffering * enabled. * ***************************************************************************************************** *ltc1403 timing from lcc28 socket board with 10mhz crystal. * *10mhz, divided from 40mhz, forced to clkin by 1403 board. * *horizontal scale is 25ns/chr or 100ns period at bclkr * *timing measured at dsp pins. jxx pin labels for jumper cable. * *bfsr pin j1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~* *bclkr pin j1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~* *bdr pin j1-26 _---_---_--- ltc1403/ltc1403a 18 1403fb applications information ; all other vector locations are free to use. when programming always be sure; the hpiint bit is unmasked (imr=200h) to allow the communications kernel and ; host pc interact. int2 should normally be masked (imr(bit 2) = 0) so that the ; dsp will not interrupt itself during a hint. hint is tied to int2 externally. ; ; ; .title vector table .mmregs reset goto #80h ;00; reset * do not modify if using debugger * nop nop nmi return_enable ;04; non-maskable external interrupt nop nop nop trap2 goto #88h ;08; trap2 * do not modify if using debugger * nop nop .space 52*16 ;0c-3f: vectors for software interrupts 18-30 int0 return_enable ;40; external interrupt int0 nop nop nop int1 return_enable ;44; external interrupt int1 nop nop nop int2 return_enable ;48; external interrupt int2 nop nop nop tint return_enable ;4c; internal timer interrupt nop nop nop brint goto breceive ;50; bsp receive interrupt nop nop nop bxint goto bsend ;54; bsp transmit interrupt nop nop nop trint return_enable ;58; tdm receive interrupt nop nop nop txint return_enable ;5c; tdm transmit interrupt nop nop int3 return_enable ;60; external interrupt int3 nop nop nop hpiint dgoto #0e4h ;64; hpiint * do not modify if using debugger * nop nop .space 24*16 ;68-7f; reserved area downloaded from: http:/// ltc1403/ltc1403a 19 1403fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) downloaded from: http:/// ltc1403/ltc1403a 20 1403fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0407 rev b printed in usa related parts part number description comments adcs ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1604 16-bit, 333ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 250ksps serial adc 5v, con? gurable bipolar/unipolar inputs ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1414 14-bit, 2.2msps parallel adc 5v supply, 2.5v span, 78db sinad ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, 14mw, msop package ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 72db sinad ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1864/ltc1865 16-bit, 250ksps serial adc 5v supply, 1 and 2 channel, 4.3mw, msop package dacs ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc1592 16-bit, serial softspan tm i out dac 1lsb inl/dnl, software selectable spans references lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1460-2.5 micropower series voltage reference 0.1% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation. downloaded from: http:/// |
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